Viranjay M. Srivastava
| 3.6 (5) |
| Sex | Male |
| Subject | VLSI design |
| Department | Electronics Engg. |
| Teaching Experience | 0-5 years |
| Teaching Status | Still Teaching |
Student reviews
Average student rating from: 5 student(s)
Good Professor
No comments
Great Sir
Viranjay Sir is a good teacher as H.R. told.
He gives good marks to those students who study carfully, and gives less marks to BUTTERing student or SOURCEfull student.
Great Sir.
Be Continue this sprit.
Amit, Satish, Sonu
Never partial about Marking
Hi,
Sir I am happy with you.
You gives marks only to working students, and not on the topper students name. As I am doing well, so i got "A"
Thanks sir,
H.R.
He is a very bad instructor
Dear Sir,
We are not moronic fools. So please stop saying .. "Ham pehle galat karenge .. fir sahi karenge !!"
You screwed our VHDL big time!
--
A sufferer student
Koool
Lol..his classes are just LOL fun..his subject and course are normally easy enough to catch up with and he is quite funny .The one hour he teaches is probably the most relaxing time of the day













